Monday, October 15, 2018

Valley Fill Passive Power Factor Correction method


Passive Power Factor Correction method

There are two types of Passive Power Factor Correction method; 
1) Capacitor Input Filter 
2) Valley Fill Power Factor Correction
Here we will discuss about Valley Fill Passive Power Factor Correction method.

Valley Fill Passive Power Factor Correction method is generally a circuit of two electrolytic capacitors, a resistor and two diodes.

The intend of the Valley Fill Passive Power Factor Correction method is to let the power converter to pull power straight off the AC line when the line voltage is larger than 50% of its peak voltage.

More details like working of Valley Fill Passive Power Factor Correction method you can find in my previous blog and the link for the same is;


Below is the circuit diagram of Valley Fill Passive Power Factor Correction method.

Power Factor Correction Method
Valley Fill Power Factor Correction Method

Selection of Component values

Now we will calculate the component values as per below specifications (consider it as an example).
VAC = 230V
VAC (min) = 90V
VAC (max) = 270V
POUT = 10W

The maximum i.e. highest bus voltage at the input of the power converter is,
VIN (max) = √2 x VAC (max)
= √2 x 270VAC
= 381.8V
= 382V
During this time, capacitors placed in  the valley fill circuit (C1 and C2) are in series and charged via the diode D2 and resistor R1.

If  the  capacitors  have  identical  capacitance  value,  the  peak  voltage  across  C1  and  C2 is;
VIN (max) / 2 = 191V
Often  a  20%  variance  in  capacitance  could  be  seen  between  like capacitors. Therefore a margin of 25% voltage rating should be considered.
Therefore the peak voltage across C1 and C2 becomes; 238.75V = 239V

Once  the  line  drops  below  50%  of  its  peak  voltage,  the  two capacitors  are  basically  placed  in parallel. The bus voltage VIN (min) is the lowermost voltage value at the power converter input.
VIN (min) at the minimum AC line voltage is,
VIN (min) = [√2 x VAC (min)] / 2
= [√2 x 90V] / 2 = 63.63V = 64V

At 60Hz, the total i.e. full time of a half AC line cycle is 8.33ms.

The power to the power converter is derived from the valley-fill capacitors when the AC line voltage is equal to or less than 50% of its peak voltage.

The  holdup  time  for  the  capacitors  equates  to;
tHOLD = (1/3) × 8.33ms  =  2.77ms

The valley-fill capacitor value can then be calculated as,
CTOTAL = {[POUT/ VIN (min)] x tHOLD} / VDROOP  
               = {[10/ 64] x 0.00277} / 20
               = {0.1562 x 0.00277} / 20
               = 0.000432 / 20
               = 0.0000216
               = 21µF
Therefore, C1 = C2 = 10µF

VDROOP is the voltage droop (drop) on the capacitors when they are delivering or supplying full power to the power converter.

Ideally VDROOP should be set to less than;
VDROOP = VIN (min) – VLED (max)
In order to ensure continuous load conduction at low line voltage.
Anyway, VDROOP is set to be 20V in the design example to avoid or prevent the need of very large valley-fill electrolytic capacitor.

A 20V VDROOP implies or indicates that the bus voltage VIN at the input of power converter will drop to 40V during part of the AC line cycle.

Let consider an example of the buck regulator, which needs VIN to be larger than the load voltage for regulation; the load will be off through part of the AC line cycle.

This has the consequence of reducing the real output load current at low AC input voltage. In this design example, the load current falls by roughly 20% from its nominal value at 90Vac.

Conclusion

Valley Fill Passive Power Factor Correction method is a low cost method for power factor improvement. This circuit can help user to achieve power factor in the range of 0.80 to 0.88.

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