Power Factor Correction (PFC) – Biasing Circuitry of L6562

We know very well what is, "Power Factor Correction" and why it is needed.
More details on "Power Factor and Power Factor Correction", you can find on my previous blog and link for the same is;

More details on "Power Factor Correction (PFC) - Critical Conduction Mode Boost Converter Calculations using L6562", you can find on my previous blog and link for the same is;

Below picture is of assembled boost circuit in a 120W power converter.

A boost circuit incorporated in a 120W power converter
Assembled boost circuit in a 120W power converter
While designing the Critical Conduction Mode boost converter we have to also focus on biasing circuitry i.e. the components which will control the working of L6562 we can say it in another words as;

Biasing Circuitry of L6562

Figure 1 shows the internal block diagram of L6562.

Internal schematic of L6562
Internal block diagram of L6562
Let’s discuss it more in detail pin by pin.

·        Pin 1 (INV): Internal schematic of L6562 shows that this pin is connected both to the inverting input of the error amplifier and to the DIS circuit block. Externally we have to connect a resistive divider between the boost regulated output voltage and this pin. The internal reference on the non-inverting input of the E/A is 2.5 V (typ), while the DIS intervention threshold is 27 µA (typ). RoutH and RoutL are then selected as follows:

RoutH = ΔVovp / 27µA = 55V / 27µA = 2.03MΩ = 2MΩ

RoutH / RoutL = Vout / 2.5V    ·    – 1 = 400V / 2.5V   ·    – 1   = 159

RoutL = RoutH / 159 = 2MΩ / 159 = 12.6kΩ

To get RoutL 12.6kΩ place 15kΩ parallel to 82kΩ.
For RoutH a resistor with a voltage rating >400 V is needed otherwise more resistors in series have to be used.

This pin can also be used as an ON/OFF control input if tied to GND by an open collector or open drain.

·        Pin 2 (COMP): This pin is the output of the error amplifier that is fed to one of the two inputs of the multiplier. Place a feedback compensation network in between this pin and INV (pin 1) having a narrow bandwidth in order to avoid the output voltage ripple (100 Hz) that would bring high distortion of the input current waveform.
We can find the capacitance value by setting the bandwidth (BW) from 20 to 30 Hz so, a capacitor can provide a low-frequency pole as well as a high DC gain.
Below equation can be use for calculating the value of single capacitor.
Ccompensation = 1 / [2π · (RoutH // RoutL) · BW]

A CRC network providing 2 poles and a zero is more suitable for constant power loads like a downstream converter.

                       The transfer functions of compensation networks are shown in Figure 2 and Figure 3;

Resistive load and Constant power load
Transfer functions of compensation networks

In our design we used combination of two capacitors and one resistor network.

CcompP = 150nF

CcompS = 2.2µF

RcompS = 22kΩ

·        Pin 3 (MULT): Internal schematic of L6562 shows that this pin is also a multiplier input. It is connected both to the output of the error amplifier and to the inverting input of PWM comparator. In application it is connected through a resistive divider, to the rectified mains to get a sinusoidal voltage reference.

The multiplier can be described by the relationship:
VCS = k · (VCOMP – 2.5V) · VMULT
VCS = It is the multiplier output. It is the reference for the current sense.
k = 0.38 (typ) is the multiplier gain.
VCOMP = It is the voltage available on Pin 2; i.e. Output of error amplifier.
VMULT = It is the voltage on pin 3.

The linear operation of the multiplier is guaranteed within the range 0 to 3 V of VMULT and the range 0 to 1.16 V (typ) of Vcs.

The procedure to properly set the operating point of the multiplier is;

First, the maximum peak value for VMULT, VMULTmax is selected. This value, which occurs at maximum mains voltage, should be 3V or nearly so in wide-range mains and less in case of single mains. The sense resistor selected is Rs = 0.55 and it is described in the detail about pin 4 of this section. The maximum peak value, occurring at maximum mains voltage is:
VMULTmax = [(ILpk · RS) / 1.1] · [VACmax / VACmin]
                     = [(1.812 · 0.55) / 1.1] · [265V/ 85V]
                     = 2.82V
Where, 1.1 V/V is the multiplier maximum slope.

The maximum required divider ratio is calculated as;
kp = (VMULTmax) / (2 · VACmax)
     = 2.82 / (1.414 · 265V)
     = 0.00752
     = 7.52 X 10¯³

Suppose a 200 μA current flowing into the multiplier divider, the lower resistor value can be calculated as;
RmultH = [(1-kp)/kp]RmultL
            = [(1 - 7.52 X 10¯³) / 7.52 X 10¯³] · 15kΩ
            = 1.97MΩ

In this application example RmultH = 2 M and RmultL = 15 k have been selected. Please note that for RmultH a resistor with a suitable voltage rating (>400 V) is needed, or more resistors in series must be used.

·        Pin 4 (CS): It is the inverting input of the current sense comparator. Instantaneous inductor current is sensed by L6562 by this pin, which is converted to a proportional voltage by an external sense resistor (Rs). As this signal crosses the threshold set by the multiplier output, the PWM latch is reset and the power MOSFET is turned off. The MOSFET stays in OFF-state until the PWM latch is reset by the ZCD signal. The pin is equipped with 200 ns leading-edge blanking to improve noise immunity.
                For 50W PFC the sense resistor value (Rs) can be calculated as follows;
RS < (VCSmin / ILpk)
RS < (1.0V / 1.812A) = 0.55
ILpk = Inductor’s maximum peak current. It is already calculated for 50W PFC solution. Please refer “Critical Conduction Mode Boost Converter Calculations using L6562”.
VCSmin = 1.0 V is the minimum voltage allowed on the L6562 current sense. It is given in the datasheet.

As the internal current sense clamping sets the maximum current that can flow in the inductor, the maximum peak of the inductor current is calculated considering the maximum voltage Vcsmax allowed on the L6562.

ILpkx = Vcsmax / RS = 1.16V / 0.55 = 2.10A
Vcsmax = 1.16V. It is given in the datasheet.
The calculated ILpkx is the limit at which the boost inductor saturates and it is used for calculating the inductor number of turns and air gap length.

The power dissipated in RS is given by;
PS = RS · (ISWRMS)² = 0.55 · (0.638A)² = 0.223W

As per the result two parallel resistors of 1.1with 0.25 W of power rating have been selected.

·        Pin 5 (ZCD): It is the input of the zero current detector circuit. In transition mode PFC, the ZCD pin is connected, through a limiting resistor, to the auxiliary winding of the boost inductor. The ZCD circuit is negative-going edge triggered. When the voltage on the pin falls below 0.7V, it sets the PWM latch and the MOSFET is turned on. Prior to falling below 0.7V, because of MOSFET’s turnoff the voltage on pin 5 must experience a positive-going edge exceeding 1.4V.

The maximum main-to-auxiliary winding turn ratio is given by;
nmax = nprimary / nauxiliary
           = [Vout – (2 · VACmax)] / 1.4V · 1.15
           = [400 – (2 · 265V)] / 1.4V · 1.15
           = 15.7
If the winding is also used for supplying the IC, the above criterion may not be well-suited with the Vcc voltage range; we have to design a self supply network.

The minimum value of the limiting resistor can be found considering the maximum voltage across the auxiliary winding with a selected turn ratio = 10 and assuming 0.8 mA current through the pin.

R1 = [(Vout/naux) – VZCDH] / 0.8mA
      = [(400V/10) – 5.7V] / 0.8mA  =  42.9k
R2 = [(2 · VACmax/naux) – VZCDL] / 0.8mA
      = [(2 · 265V/10) – 0V] / 0.8mA = 46.8k

VZCDH = 5.7 V and VZCDL = 0 V are the upper and lower ZCD clamp voltages of the L6562.
               Considering the higher value between the two calculated, RZCD = 47 k has been selected as the limiting resistor.

·        Pin 6 (GND): This pin acts as the current return both for the signal internal circuitry and for the gate drive current. When laying out the printed circuit board, these two paths should run separately.

·        Pin 7 (GD): It is the output of the L6562. The pin is able to drive an external MOSFET with 600 mA source and 800 mA sink capability. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. An internal pull-down circuit holds the pin low to avoid undesired switch-on of the external MOSFET because of some leakage current when the supply of the L6562 is below the UVLO threshold.

·        Pin 8 (VCC): At this pin supply is applied to make run L6562. This pin is externally connected to the startup circuit and to the self-supply circuit. To start the L6562, the voltage must exceed the startup threshold (typically 12.5 V). High value startup resistors (in the hundreds kΩ), should be use for reducing power consumption and optimizes system efficiency at low load. If the Vcc voltage exceeds 25V, an internal clamping circuitry, is activated in order to clamp the voltage.

Below figure shows location of biasing components in PFC Boost circuit using L6562.

Biasing components in PFC Boost circuit
Location of biasing components in PFC Boost circuit using L6562
Below pictures are of a boost circuit assembly on general board and it’s measured output voltage on Agilent DSO-X 2024A.

Assembled L6562A based boost circuit
L6562A based boost circuit assembled on general board for testing

Output of the Boost Circuit using L6562
Output of the Boost Circuit using L6562 measured on Agilent DSO-X 2024A

Reference : Referred STMicroelectronics "Solution for designing a transition mode PFC preregulator with the L6562A". Link is embed in title.

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